Shou-Li Hsu

Shou-Li Hsu

Shou-Li Hsu is a talented circuit designer from Taiwan, experienced in CPU design and VLSI. He's currently working as a CPU RTL design engineer in a tech company.

Verilog and SystemVerilog Integer Data Types for Beginners

This tutorial gives a comprehensive overview of Verilog and SystemVerilog's nine integer data types, 2-state and 4-state data types, and signed and unsigned integer types. It also offers examples of declaring variables of different SystemVerilog integer data types.

Understanding Verilog and SystemVerilog Net Types

Net types in Verilog and SystemVerilog are used to represent connections between elements in a circuit design. They can be built-in or user-defined and serve different functions.

Verilog and SystemVerilog Data Types: A Comprehensive Guide

Learn about the comprehensive guide to Verilog and SystemVerilog data types, including nets, variables, constants, vector, integer, real, string, event, user-defined data types, enumerations, structures, unions, packed and unpacked arrays, and best practices for their usage.

Installing Icarus Verilog (Iverilog): A Quick Guide

Learn how to install Icarus Verilog (Iverilog), a free and open-source simulator for digital circuit design and verification, on your Linux or macOS system. Test your installation with a "Hello, World!" program in SystemVerilog.

Installing Vivado ML 2022.2: A Guide for FPGA Designers

In this guide, we will walk you through the process of installing Vivado ML 2022.2, a powerful FPGA design tool from Xilinx. Learn about system requirements, downloading the software, and step-by-step installation instructions.

Circuit Design Tool Guide: Navigating the Digital Seas

Discover essential digital circuit design tools like behavioral simulation, synthesis, place and route, and FPGA design. Popular tools include ModelSim, VCS, Design Compiler, Innovus, Vivado, and Quartus Prime. Learn how these tools work together to create reliable and efficient circuits.

Designing a Synchronous FIFO in Verilog and SystemVerilog

Learn how to design a synchronous FIFO buffer in Verilog and SystemVerilog, an essential component for managing data flow and ensuring efficient data processing in digital systems.

Round-Robin Arbiter Design in Verilog and SystemVerilog

Round-robin arbiter manages multiple requests for a shared resource. It prevents starvation and ensures statistical fairness. Its design utilizes two fixed priority arbiters and mask update logic to promote fairness.

Designing an Arbiter in Verilog and SystemVerilog

Learn how to design an arbiter in Verilog and SystemVerilog. This post covers the implementation of a fixed priority arbiter using always_comb and for loop to select the highest priority requester.

Designing an FIR Filter in Verilog and SystemVerilog

Learn how to design Finite Impulse Response (FIR) filters in Verilog and SystemVerilog. This post covers basic and pipelined filters to improve performance.