Understanding Verilog and SystemVerilog Net Types

If you are learning circuit design, you may have come across the term "net types" in Verilog and SystemVerilog. Net types represent physical connections between structural entities, such as gates. In this tutorial, we will discuss the different types of net types and their functions.

What Are Net Types?

Net types are a way of representing connections between elements in a circuit design. A net does not store a value, but instead, its value is determined by the values of its drivers. Net types can be divided into two categories: built-in and user-defined.

Built-In Net Types in Verilog and SystemVerilog

There are several types of built-in net types in Verilog and SystemVerilog, as shown in the following table. These include wire, tri, tri0, tri1, supply0, supply1, wand, wor, triand, trior, and trireg.

User-Defined Net Types in SystemVerilog

SystemVerilog supports user-defined net types which enable the definition of custom, abstract values for a wire, including its resolution function. These net types provide a name for a specific data type, and optionally a corresponding resolution function, which is then used by nets declared with the user-defined net type.

Types of Built-In Net Types in Verilog and SystemVerilog

Wire and Tri Nets in Verilog and SystemVerilog

wire and tri nets are used to connect elements in a circuit design. A wire net can be used for nets that are driven by a single gate or continuous assignment. A tri net type can be used where multiple drivers drive a net. Logical conflicts from multiple sources of the same strength on a wire or a tri net result in x (unknown) values.

Unresolved Nets in Verilog and SystemVerilog

An unresolved or unidriver wire (uwire) is used to model nets that allow only a single driver. The uwire type can be used to enforce this restriction. It shall be an error to connect any bit of a uwire net to more than one driver.

Wired Nets in Verilog and SystemVerilog

Wired nets are of type wor, wand, trior, and triand and are used to model wired logic configurations. Wired nets use different truth tables to resolve the conflicts that result when multiple drivers drive the same net. The wor and trior nets shall create wired OR configurations so that when any of the drivers is 1, the resulting value of the net is 1. The wand and triand nets shall create wired AND configurations so that if any driver is 0, the value of the net is 0.

Trireg Nets in Verilog and SystemVerilog

The trireg net stores a value and is used to model charge storage nodes. A trireg net can be in one of two states: the driven state or the capacitive state. The strength of the value on the trireg net in the capacitive state can be small, medium, or large, depending on the size specified in the declaration of the trireg net. The strength of a trireg net in the driven state can be supply, strong, pull, or weak, depending on the strength of the driver.

Tri0 and Tri1 Nets in Verilog and SystemVerilog

tri0 and tri1 nets model nets with resistive pulldown and resistive pullup devices, respectively. A tri0 net is equivalent to a wire net with a continuous 0 value of pull strength driving it. A tri1 net is equivalent to a wire net with a continuous 1 value of pull strength driving it. When no driver drives a tri0 net, its value is 0 with strength pull. When no driver drives a tri1 net, its value is 1 with strength pull.

Supply Nets in Verilog and SystemVerilog

supply0 and supply1 nets can be used to model the power supplies in a circuit. These nets shall have supply strengths.

User-Defined Nettypes in SystemVerilog

SystemVerilog introduced the feature of user-defined nettypes, enabling the creation of custom, abstract values for a wire, including its resolution function. Essentially, user-defined nettypes allow the definition of a custom type of net in SystemVerilog.

To define a user-defined nettype, you need to create a resolution function that computes the value of the net based on the values of its drivers. Here's an example of a resolution function that finds the maximum value of its input drivers:

function automatic logic [7:0] maxValue(input logic [7:0] drivers[]);
  logic [7:0] max = '0;
  foreach (drivers[i]) begin
    if (drivers[i] > max) max = drivers[i];
  end
  return max;
endfunction

In this example, the function is called maxValue and it takes an input array of 8-bit logic values called drivers. It returns a single 8-bit logic value that represents the maximum value of the input drivers.

To associate the maxValue function with a custom nettype called MyNettype, you can use the nettype keyword in SystemVerilog, like this:

nettype logic [7:0] MyNettype with maxValue;

In this example, the data type for the nettype is logic [7:0], which is an 8-bit logic value. The with keyword is used to associate the maxValue function with the MyNettype nettype.

Once you've defined a user-defined nettype, you can use it to declare nets in your design. Here's an example of how to declare a MyNettype net and assign values to its drivers:

MyNettype myNet;
logic [7:0] driverValues[3] = '{8'hFF, 8'h55, 8'hAA};
assign myNet = driverValues;

In this example, we declare a MyNettype net called myNet. We also declare an array of 8-bit logic values called driverValues and assign it three values. Finally, we assign the myNet net the value computed by the maxValue function based on the values of the driverValues array.

With user-defined nettipes, you can create more complex and abstract types of nets that suit the needs of your specific design.

Conclusion

In conclusion, understanding net types is an essential part of learning Verilog and SystemVerilog. The built-in net types are wire, tri, tri0, tri1, supply0, supply1, wand, wor, triand, trior, and trireg, while user-defined net types provide more general abstract values for a wire. Understanding the functions of these net types will help you create a circuit design that is efficient and effective.