Understanding $strobe in SystemVerilog and Verilog: A Practical Guide

Hey there! Today, I want to delve into a topic in SystemVerilog that often goes unnoticed but is incredibly useful: the $strobe system task. If you've ever wondered how it differs from $display or $write, you're not alone. Let's break it down and understand its unique advantages.

What is $strobe?

In SystemVerilog, $strobe is a system task that resembles $display and $write. You might have used those for debugging or to check the state of your simulation at specific moments. The crucial difference lies in the timing of their execution: while $display and $write execute immediately, $strobe waits until the end of the current simulation time step to execute.

When to Use $strobe?

So, when is it appropriate to use $strobe? Consider a sequential module, such as an accumulator, that updates its value on a clock edge. Here’s a simple example:

module Accumulator(
  input  logic       clk,
  input  logic       rst,
  input  logic [7:0] in,
  output logic [7:0] out
);
  always @(posedge clk) begin
    if (rst)
      out <= 0;
    else
      out <= out + in;
  end
endmodule

Now, let's add some debug statements using $display and $strobe to observe their behavior:

always @(posedge clk or posedge rst) begin
  if (rst)
    out <= 0;
  else
    out <= out + in;
    
  $display("Time: %0t | $display: out = %0d", $time, out);
  $strobe("Time: %0t | $strobe: out = %0d", $time, out);
end

What’s Going On?

When you run this simulation, $display prints the value of out before the clock edge updates it. This is because, in SystemVerilog’s event scheduling, the always block runs in the Active region first, so $display executes immediately. The non-blocking assignment (out <= out + in;) then happens in the Nonblocking Assign Update region, updating out. Finally, $strobe runs in the Postponed region, after all other events in the current time step, displaying the updated value of out.

SystemVerilog’s event scheduling can be intricate, but the key takeaway is this: $display shows the value at the point of its execution, while $strobe shows the value after all updates in the current time step.

Practical Insights

Using $strobe can be especially beneficial when you need to verify the final value of variables after all operations for the current time step are complete. It's akin to having a final check at the end of the simulation slice, giving you the most accurate state of your variables.

$strobe is a powerful addition to your SystemVerilog toolkit, particularly useful for debugging and understanding the final values of your variables after all events in a time step. The next time you encounter unexpected values in your simulation, try using $strobe to gain clearer insights.