Global Clocking Sampled Value Functions in Verilog and SystemVerilog

In this blog post, we'll dive into global clocking sampled value functions in Verilog and SystemVerilog. These functions are essential for accessing past and future sampled values of an expression, particularly when global clocking is defined. By the end of this post, you'll have a better understanding of the various global clocking sampled value functions and how to utilize them in your designs. If you're not familiar with the basic sampled value functions, we recommend reading our previous post, Acing Verilog and SystemVerilog Sampled Value Functions, before continuing.

Before we start, it's essential to define a global clocking block for the functions to make sense. Here's an example:

module top;
  logic clk;
  global clocking sys @(posedge clk); endclocking
  // ...
endmodule

Global Clocking Past Sampled Value Functions

$past_gclk: Accessing Past Sampled Values

The $past_gclk(expression) function allows you to access the past sampled value of an expression at the previous global clock tick.

Example:

module PastGclkExample (
  input wire clk,
  input wire rst,
  input wire stickyIn
);
  global clocking sys @(posedge clk); endclocking

  a1: assert property (@$global_clock $past_gclk(stickyIn) |-> $stable_gclk(stickyIn))
    else $error("Sticky input changed unexpectedly");
endmodule

$rose_gclk: Detecting Rising Edges

The $rose_gclk(expression) function detects when a signal's least significant bit (LSB) transitions from 0 to 1 at the previous global clock tick.

Example:

module RoseGclkExample (
  input wire clk,
  input wire rst,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a2: assert property (@$global_clock $rose_gclk(dataIn) |-> $stable_gclk(rst))
    else $error("Data input rose while reset is unstable");
endmodule

$fell_gclk: Detecting Falling Edges

The $fell_gclk(expression) function detects when a signal's LSB transitions from 1 to 0 at the previous global clock tick.

Example:

module FellGclkExample (
  input wire clk,
  input wire rst,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a3: assert property (@$global_clock $fell_gclk(dataIn) |-> $stable_gclk(rst))
    else $error("Data input fell while reset is unstable");
endmodule

$stable_gclk: Checking Signal Stability

The $stable_gclk(expression) function checks whether a signal's value has remained unchanged at the previous global clock tick.

Example:

module StableGclkExample (
  input wire clk,
  input wire rst,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a4: assert property (@$global_clock $stable_gclk(clk) |-> $stable_gclk(dataIn))
    else $error("Data input changed when clock is stable");
endmodule

$changed_gclk: Detecting Signal Changes

The $changed_gclk(expression) function checks whether a signal's value has changed at the previous global clock tick.

Example:

module ChangedGclkExample (
  input wire clk,
  input wire rst,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a5: assert property (@$global_clock $changed_gclk(dataIn) |-> $past_gclk(dataIn) !== dataIn)
    else $error("Data input did not change as expected");
endmodule

Global Clocking Future Sampled Value Functions

$future_gclk: Obtain the Next Sampled Value

The $future_gclk function returns the sampled value of an expression at the next global clock tick. This can be useful when verifying the behavior of your design based on the future value of a signal.

module FutureGclkExample(
  input wire clk,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a6: assert property (@$global_clock $future_gclk(dataIn) !== dataIn) 
    else $error("Data input does not change at the next global clock tick");
endmodule

$rising_gclk: Detect a Rising Transition

The $rising_gclk function returns true if the least significant bit (LSB) of the expression changes to 1 at the next global clock tick; otherwise, it returns false.

module RisingGclkExample(
  input wire clk,
  input wire signalIn
);
  global clocking sys @(posedge clk); endclocking

  a7: assert property (@$global_clock $rising_gclk(signalIn)) 
    else $error("Signal did not have a rising transition at the next global clock tick");
endmodule

$falling_gclk: Detect a Falling Transition

The $falling_gclk function returns true if the least significant bit (LSB) of the expression changes to 0 at the next global clock tick; otherwise, it returns false.

module FallingGclkExample(
  input wire clk,
  input wire signalIn
);
  global clocking sys @(posedge clk); endclocking

  a8: assert property (@$global_clock $falling_gclk(signalIn)) 
    else $error("Signal did not have a falling transition at the next global clock tick");
endmodule

$steady_gclk: Check for No Change at the Next Tick

The $steady_gclk function returns true if the sampled value of the expression does not change at the next global clock tick; otherwise, it returns false.

module SteadyGclkExample(
  input wire clk,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a9: assert property (@$global_clock $steady_gclk(dataIn)) 
    else $error("Data input changes at the next global clock tick");
endmodule

$changing_gclk: Check for a Change at the Next Tick

The $changing_gclk function is the complement of $steady_gclk, meaning it returns true if the sampled value of the expression changes at the next global clock tick; otherwise, it returns false.

module ChangingGclkExample(
  input wire clk,
  input wire dataIn
);
  global clocking sys @(posedge clk); endclocking

  a10: assert property (@$global_clock $changing_gclk(dataIn)) 
    else $error("Data input does not change at the next global clock tick");
endmodule

In conclusion, global clocking sampled value functions in Verilog and SystemVerilog provide a powerful way to write concise and effective assertions, assumptions, and covers. By using these functions, you can ensure your design behaves as intended with respect to global clock transitions and sample values, making your verification process more efficient and reliable.