A Brief History of SystemVerilog

Introduction

Hardware Description Languages (HDLs) have become essential tools for digital design engineers in the semiconductor industry. SystemVerilog is a high-level hardware description language that has evolved significantly over the years to become one of the most popular languages for IC design and verification.

Verilog HDL and its Evolution

Verilog HDL was invented in the 1980s by Phil Moorby and Prabhu Goel as a proprietary hardware modeling language. It was owned by Gateway Design Automation Inc., and was extensively modified between 1984 and 1990. In 1990, Cadence Design Systems acquired Gateway and put Verilog into the public domain under the name Open Verilog International (OVI). Verilog HDL became IEEE Std. 1364-1995 in December 1995. A significantly revised version was published in 2001: IEEE Std. 1364-2001. In 2005, various extensions and modifications to Verilog were adopted, resulting in the IEEE Std. 1364-2005, or Verilog-2005.

The Birth and Evolution of SystemVerilog

In 1997, Co-Design Automation was established by Simon Davidmann, Peter Flake, and Phil Moorby with the aim of creating a new language and simulator. Their original vision was to develop a unified language, Superlog (derived from Super and Verilog), for system specification, hardware design, hardware verification, and software development. However, Superlog was later renamed to SystemVerilog as it gained wider adoption by Accellera and became an IEEE standard.

The Journey to IEEE Standardization

In 2002, Co-Design Automation donated the Superlog language to Accellera, and the bulk of the verification functionality was based on the OpenVera language, which was donated by Synopsys. SystemVerilog was later adopted as IEEE Std. 1800-2005 in 2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, resulting in the creation of IEEE Std. 1800-2009. The current version of the standard is IEEE Std. 1800-2017. Over time, SystemVerilog has evolved to become a comprehensive hardware description and verification language with a broad range of features, making it an important tool for the semiconductor industry.

Conclusion

In conclusion, SystemVerilog has a rich history and has evolved significantly over the years to become one of the most popular languages for IC design and verification. It extends Verilog and adds many new features and capabilities to aid design verification. Its widespread use has changed the role of design engineers, who must be able to craft system-level behavioral circuit definitions that provably meet design requirements and must understand synthesis and other CAD tool processes so that results can be critically examined and interpreted.