Designing Sign Extension Logic in Verilog and SystemVerilog

Sign extension is a common operation in digital circuits where a value with a smaller bit width is expanded to a larger bit width while preserving its sign. In this tutorial, we will design a module for sign extension in Verilog and SystemVerilog.

Sign Extension Overview

In digital circuits, sign extension is typically used when a value needs to be expanded to a larger bit width, but the original value is stored with fewer bits. The sign bit, which indicates whether the number is positive or negative, is duplicated to fill the additional bits. This process ensures that the original value is preserved while increasing the bit width.

The opposite operation of sign extension is called zero extension. In zero extension, the additional bits are filled with zeros instead of duplicating the sign bit.

Designing a Sign Extension Module in Verilog and SystemVerilog

To implement sign extension in Verilog and SystemVerilog, we will use a module with two parameters: InputWidth and OutputWidth. The InputWidth parameter specifies the width of the input value, and the OutputWidth parameter specifies the width of the output value. We will assume that the input value is stored as a two's complement signed integer.

module SignExtension #(
  parameter InputWidth  = 8,
  parameter OutputWidth = 16
) (
  input  logic signed [InputWidth-1:0]  in,
  output logic signed [OutputWidth-1:0] out
);

  assign out = { {OutputWidth-InputWidth{in[InputWidth-1]}}, in };

endmodule

The SignExtension module has the following ports:

• in: the input value to be sign-extended
• out: the sign-extended output value

The module takes the input value in and extends it to the output width OutputWidth. The sign bit of the input value is duplicated to fill the additional bits in the output value. The {OutputWidth-InputWidth{in[InputWidth-1]}} expression creates a vector of OutputWidth-InputWidth bits, where each bit is set to the value of the sign bit of the input value. This vector is then concatenated with the input value to create the output value.

Conclusion

In this tutorial, we designed a sign extension module in Verilog and SystemVerilog. Sign extension is a common operation in digital circuits and is used to expand a value to a larger bit width while preserving its sign. The module we designed takes an input value and sign-extends it to the specified output width. The sign extension module can be used as a building block for more complex digital circuits, such as processors and memory systems.