Designing Shift Registers in Verilog and SystemVerilog

Shift registers are commonly used in digital circuits to store and shift data. In this tutorial, we will design a simple shift register using Verilog and SystemVerilog.

Shift Register Overview

A shift register is a sequential digital circuit that can shift a stored data value by one or more positions. The simplest shift register is a single-bit, serial-in/serial-out (SISO) register, which takes in one bit of data at a time and shifts it through the register. A parallel-in/parallel-out (PIPO) shift register, on the other hand, can load and output multiple bits at once.

In this tutorial, we will be designing a 4-bit PIPO shift register that can shift data to the left or right based on a control signal.

Designing Shift Registers in Verilog and SystemVerilog

We will implement the 4-bit PIPO shift register in Verilog and SystemVerilog using the following module:

module ShiftRegister #(
  parameter Width = 4
) (
  input  logic             clk,
  input  logic             rstN,
  input  logic             shiftRight,
  input  logic [Width-1:0] dataIn,
  output logic [Width-1:0] dataOut
);

  logic [Width-1:0] shiftRegisters;

  always_ff @(posedge clk, negedge rstN) begin
    if (~rstN) begin
      shiftRegisters <= '0;
    end
    else if (shiftRight) begin
      shiftRegisters <= {shiftRegisters[0], shiftRegisters[Width-1:1]};
    end
    else begin
      shiftRegisters <= {shiftRegisters[Width-2:0], shiftRegisters[Width-1]};
    end
  end

  assign dataOut = shiftRegisters;

endmodule

The ShiftRegister module now has the following ports:

• clk: the clock signal
• rstN: the active-low reset signal
• shiftRight: the control signal that determines the direction of the shift (0 for left, 1 for right)
• dataIn: the input data to be loaded into the shift register
• dataOut: the output data from the shift register

The Width parameter sets the number of bits in the shift register.

The shiftRegisters signal is a Width-bit vector that stores the current state of the shift register. The always_ff block updates the shift registers on the positive edge of the clock or negative edge of the reset signal, depending on whether the shift direction is left or right.

If the reset signal is asserted, the shift register is cleared to 0. If the shift direction is right, the shiftRegisters signal is shifted to the right by one bit, with the least significant bit being filled with a 0. If the shift direction is left, the shiftRegisters signal is shifted to the left by one bit, with the most significant bit being filled with a 0.

The dataOut signal is assigned to the current value of the shiftRegisters signal, which represents the output of the shift register.

Conclusion

In this tutorial, we designed a simple 4-bit PIPO shift register using Verilog and SystemVerilog. We demonstrated how to use Verilog and SystemVerilog to implement sequential logic and how to control the behavior of the shift register using a control signal. This shift register can be used as a building block for more complex digital circuits, such as shift registers with parallel load or serial input/output.