Designing Latches in Verilog and SystemVerilog

Latches are sequential logic circuits that store data and can change their output based on the current input or previous state. In this tutorial, we will use Verilog and SystemVerilog to design a simple latch using the always_latch construct.

Latch Overview

A latch is a level-sensitive memory element that retains its output state based on the input signal, even after the input signal is removed. It has two stable states, set and reset. The output of a latch changes only when its input changes while the enable input is active.

Designing Latch in Verilog and SystemVerilog

We will implement a simple level-sensitive latch using the always_latch construct. Here is the code:

module Latch (
  input  logic clk,
  input  logic enable,
  input  logic dataIn,
  output logic dataOut
);

  always_latch @(posedge clk) begin
    if (enable) begin
      dataOut <= dataIn;
    end
  end

endmodule

If you are designing the latch with pure Verilog, replace the always_latch keyword with always.

The Latch module has the following ports:

• clk: the clock signal
• enable: the enable signal for the latch
• dataIn: the input data to be stored in the latch
• dataOut: the output data from the latch

The always_latch block is used to implement the latch. It is triggered on the positive edge of the clock and retains the output state until the next clock edge. The latch is enabled when the enable signal is high. When the enable signal is low, the output of the latch remains unchanged.

The dataIn signal is stored in the latch and is available at the dataOut output port. If the enable signal is low, the output of the latch retains its previous state.

Conclusion

In this tutorial, we learned how to design a simple level-sensitive latch in Verilog and SystemVerilog using the always_latch or always construct. Latches can be used as building blocks for more complex digital circuits, such as counters and shift registers. It is important to note that latches are not recommended for use in synchronous designs, and flip-flops should be used instead.