Designing Finite State Machines in Verilog and SystemVerilog

A finite state machine (FSM) is a mathematical model used to describe and design digital circuits and systems that exhibit a certain behavior. In this tutorial, we will learn how to design finite state machines in Verilog and SystemVerilog, a hardware description language widely used for digital design.

Designing a Moore Machine in Verilog and SystemVerilog

A Moore machine's output is solely dependent on the current state. To design a Moore machine in Verilog and SystemVerilog, we will first define a State enum that represents the different states of the machine. We will then use this enum to implement the logic for each state using a case statement. Here's an example code snippet:

typedef enum {
  S0,
  S1,
  S2
} State;

module MooreMachine (
  input  logic clk, rstN, in,
  output logic out
);

  State state, stateNext;

  always_ff @(posedge clk or negedge rstN) begin
    if (!rstN) begin
      state <= S0;
    end
    else begin
      state <= stateNext;
    end
  end

  always_comb begin
    case (state)
      S0: begin
        out = 1'b0;
        stateNext = in ? S1 : S0;
      end
      S1: begin
        out = 1'b1;
        stateNext = in ? S2 : S0;
      end
      S2: begin
        out = 1'b0;
        stateNext = in ? S2 : S0;
      end
      default: begin
        out = '0;
        stateNext = S0;
      end
    endcase
  end

endmodule

In this example, we define a module named MooreMachine that takes an input signal in, a clock signal clk, a reset signal rstN, and generates an output signal out. Inside the always_ff block, we update the current state based on the next state when rstN is active low. Inside the always_comb block, we use a case statement to implement the logic for each state. Note that the output signal is solely dependent on the current state. We also use state and stateNext signals to represent the current and next state of the machine, respectively. In the case statement, we use begin ... end to group multiple statements inside each state.

Designing a Mealy Machine in Verilog and SystemVerilog

A Mealy machine's output is dependent on both the current state and the input. To design a Mealy machine in Verilog and SystemVerilog, we will use the same approach as the Moore machine. Here's an example code snippet:

typedef enum {
  S0,
  S1,
  S2
} State;

module MealyMachine (
  input  logic clk, rstN, in,
  output logic out
);

  State state, stateNext;

  always_ff @(posedge clk or negedge rstN) begin
    if (!rstN) begin
      state <= S0;
    end
    else begin
      state <= stateNext;
    end
  end

  always_comb begin
    case (state)
      S0: begin
        out = in ? 1'b0 : 1'b1;
        stateNext = in ? S1 : S0;
      end
      S1: begin
        out = 1'b0;
        stateNext = in ? S2 : S0;
      end
      S2: begin
        out = in ? 1'b1 : 1'b0;
        stateNext = S0;
      end
      default: begin
        out = '0;
        stateNext = S0;
      end
    endcase
  end

endmodule

In this example, we define a module named MealyMachine that takes an input signal in, a clock signal clk, a reset signal rstN, and generates an output signal out. Inside the always_ff block, we update the current state based on the next state when rstN is active low. Inside the always_comb block, we use a case statement to implement the logic for each state. Note that the output signal is dependent on both the current state and the input. We also use state and stateNext signals to represent the current and next state of the machine, respectively. In the case statement, we use begin ... end to group multiple statements inside each state.

Conclusion

In this tutorial, we learned how to design finite state machines in Verilog and SystemVerilog. We covered the two types of state machines, Moore machine and Mealy machine, and demonstrated how to implement each type using a case statement. We also used an enum to define the different states of the machine, and showed how to use always_ff to update the state, and always_comb to implement the logic for each state.

Finite state machines are fundamental building blocks in digital circuit design and are used in many applications such as control systems, digital signal processing, and communication systems. By mastering the design of finite state machines in Verilog and SystemVerilog, you can design more complex digital systems and circuits that meet specific behavior requirements.