Designing Frequency Dividers in Verilog and SystemVerilog

A frequency divider is a digital circuit that divides the frequency of an input clock signal to produce an output signal with a lower frequency. In this tutorial, we will discuss how to design frequency dividers in Verilog and SystemVerilog, including examples of dividing by 2, 4, and 3.

Overview of Frequency Dividers

A frequency divider is a fundamental building block in digital circuits, used to reduce the frequency of a clock signal to a lower frequency. Frequency dividers are commonly used in applications such as data synchronization, frequency synthesis, and digital communication.

Designing a Divide by 2 Frequency Divider in Verilog and SystemVerilog

The following code shows an example implementation of a divide by 2 frequency divider in Verilog and SystemVerilog:

module DivideBy2 (
  input  logic clk,
  input  logic rstN,
  output logic clkOut
);

  always_ff @(posedge clk or negedge rstN) begin
    if (!rstN) begin
      clkOut <= 0;
    end
    else begin
      clkOut <= ~clkOut;
    end
  end

endmodule

The DivideBy2 module has three ports: clk, rstN, and clkOut. The clk port is the input clock signal to be divided, the rstN port is an active-low reset signal, and the clkOut port is the output clock signal with half the frequency of the input signal. The always_ff block is used to describe the behavior of the divide by 2 frequency divider. When a rising edge is detected in the input signal, the clkOut output signal is toggled, unless the reset signal is asserted.

Designing a Divide by 4 Frequency Divider in Verilog and SystemVerilog

A divide by 4 frequency divider can be implemented by using a divide by 2 frequency divider twice in series, as shown in the following code:

module DivideBy4 (
  input  logic clk,
  input  logic rstN,
  output logic clkOut
);

  logic clkOutDiv1;

  DivideBy2 divideBy2_1 (
    .clk(clk),
    .rstN(rstN),
    .clkOut(clkOutDiv1)
  );

  DivideBy2 divideBy2_2 (
    .clk(clkOutDiv1),
    .rstN(rstN),
    .clkOut(clkOut)
  );

endmodule

The DivideBy4 module has the same ports as the DivideBy2 module, but it uses two DivideBy2 instances in series to divide the frequency by 4. The clkOutDiv1 signal is used to connect the output of the first DivideBy2 instance to the input of the second DivideBy2 instance.

Designing a Divide by 3 Frequency Divider in Verilog and SystemVerilog

A divide by 3 frequency divider is more complex to implement compared to divide by 2 or 4 frequency dividers, because it cannot be achieved by simply cascading multiple divide by 2 or divide by 4 frequency dividers. However, it can be implemented using a counter and a comparator.

One possible implementation of a divide by 3 frequency divider is to use a counter to keep track of the number of clock cycles, and a comparator to detect when the counter reaches a certain threshold value. When the threshold is reached, the counter is reset and the output clock signal is toggled.

The following code shows an example implementation of a divide by 3 frequency divider in Verilog/SystemVerilog with a reset signal:

module DivideBy3 (
  input  logic clk,
  input  logic rstN,
  output logic clkOut
);

  logic [1:0] count;

  always_ff @(posedge clk or negedge rstN) begin
    if (!rstN) begin
      count  <= 0;
      clkOut <= 0;
    end
    else begin
      count <= count + 1;
      if (count == 2'b10) begin
        count  <= 0;
        clkOut <= ~clkOut;
      end
    end
  end

endmodule

The DivideBy3 module has three ports: clk, rstN, and clkOut. The clk port is the input clock signal to be divided, the rstN port is an active-low reset signal, and the clkOut port is the output clock signal with one-third the frequency of the input signal.

The always_ff block is used to describe the behavior of the divide by 3 frequency divider. The count signal is a 2-bit counter that counts the number of clock cycles. When the counter reaches a threshold of 2, the counter is reset and the output clock signal is toggled.

Conclusion

In conclusion, frequency dividers are essential building blocks in digital circuits that can be used in various applications, such as frequency synthesis, data synchronization, and digital communication. We discussed how to design divide by 2, 4, and 3 frequency dividers in Verilog and SystemVerilog, and we showed how a divide by 3 frequency divider can be implemented using a counter and a comparator. With the knowledge gained from this tutorial, you should be able to implement frequency dividers for your own digital designs.