Designing Edge Detectors in Verilog and SystemVerilog

Edge detectors are a fundamental building block in digital circuits, used to detect rising or falling edges of a signal. In this tutorial, we will discuss how to design edge detectors in Verilog and SystemVerilog, including examples of both rising and falling edge detectors, as well as a both edge detector.

Overview of Edge Detectors

An edge detector is a digital circuit that detects transitions in a signal, such as a rising or falling edge. Edge detectors are commonly used in applications such as clock synchronization, data sampling, and digital communication.

Designing a Rising Edge Detector in Verilog and SystemVerilog

The following code shows an example implementation of a rising edge detector in Verilog and SystemVerilog:

module RisingEdgeDetector (
  input  logic clk,
  input  logic signal,
  output logic edge
);

  logic signalPrev;

  always_ff @(posedge clk) begin
    signalPrev <= signal;
    edge       <= (signal && !signalPrev);
  end

endmodule

The RisingEdgeDetector module has three ports: clk, signal, and edge. The clk port is the clock input, the signal port is the input signal to detect the rising edge, and the edge port is the output signal that is high for one clock cycle when a rising edge is detected.

The signalPrev signal is used to store the previous value of the input signal. The always_ff block is used to describe the behavior of the rising edge detector. When a rising edge is detected, the edge output is set high for one clock cycle.

Designing a Falling Edge Detector

A falling edge detector can be implemented by inverting the input signal and the previous signal, as shown in the following code:

module FallingEdgeDetector (
  input  logic clk,
  input  logic signal,
  output logic edge
);

  logic signalPrev;

  always_ff @(posedge clk) begin
    signalPrev <= signal;
    edge       <= (!signal && signalPrev);
  end

endmodule

The FallingEdgeDetector module has the same ports as the RisingEdgeDetector module, but the behavior of the edge detector is inverted. When a falling edge is detected, the edge output is set high for one clock cycle.

Designing a Both Edge Detector

A both edge detector is a digital circuit that detects both rising and falling edges. The following code shows an example implementation of a both edge detector in Verilog and SystemVerilog using an XOR gate:

module BothEdgeDetector (
  input  logic clk,
  input  logic signal,
  output logic edge
);

  logic signalPrev;

  always_ff @(posedge clk) begin
    signalPrev <= signal;
    edge       <= signal ^ signalPrev;
  end

endmodule

The BothEdgeDetector module has the same ports as the RisingEdgeDetector and FallingEdgeDetector modules. The always_ff block is used to describe the behavior of the both edge detector. The XOR gate is used to compare the current and previous signal values. When either a rising or falling edge is detected, the edge output is set high for one clock cycle.

Using an XOR gate to implement a both edge detector has the advantage of being simpler and more concise than using an OR gate. It also eliminates the need for an inverter to complement the signalPrev signal, as required in the OR gate implementation.

Conclusion

In this tutorial, we discussed how to design rising and falling edge detectors, as well as a both edge detector in Verilog and SystemVerilog. By building your edge detectors, you can achieve more precise control over your signals and enable more advanced functionality in your digital circuits. Edge detectors are essential in various digital applications, such as signal processing and data acquisition.