Guide to Verilog and SystemVerilog Constants

Last updated on Apr 12, 2023

Verilog and SystemVerilog constants are a fundamental concept in hardware design, allowing designers to create flexible, robust, and easily modifiable designs. In this tutorial, we'll explore the different types of Verilog and SystemVerilog constants, including parameter, localparam, specparam, type parameter, and const constants.

Parameter Constants in Verilog and SystemVerilog

Parameter constants are values defined at the elaboration time and cannot be changed during runtime. They have a value, a type, and a range specification, which default to the type and range of the assigned value if not specified. Parameter constants are declared in the body of a module, interface, program, class, or package, and can also be declared in a parameter port list.

Here are some basic examples of how to define parameter constants in Verilog and SystemVerilog:

// Example 1: defining a parameter constant with a value of 5
parameter int MyParam = 5;

// Example 2: defining a parameter constant with a range specification and a value of 8'hFF
parameter [7:0] MyParam = 8'hFF;

// Example 3: defining a parameter constant with a type specification and a value of 42
parameter int MyParam = 42;

In the first example, we define a parameter constant named MyParam with a value of 5. This parameter can be used throughout the design and cannot be changed during runtime.

In the second example, we define a parameter constant named MyParam with a range specification of [7:0] and a value of 8'hFF. This parameter is declared as an 8-bit wide vector with all bits set to 1.

In the third example, we define a parameter constant named MyParam with a type specification of int and a value of 42. This parameter is declared as an integer value and can be used in arithmetic operations within the design.

Here's an example of a Mux module that has a parameter to set the width of its input ports:

module Mux #(parameter int Width = 8)
(
  input  logic [Width-1:0] a,
  input  logic [Width-1:0] b,
  input  logic sel,
  output logic c
);
  // Mux implementation here
endmodule

In this example, the Mux module has a parameter named Width with a default value of 8. This parameter is used to set the width of the input ports a and b, which are declared as logic [Width-1:0]. The sel and c ports are declared as logic and do not use the Width parameter.

You can instantiate the Mux module with a specific width value like this:

Mux #(4) myMux (a, b, sel, c);

In this example, we are instantiating the Mux module with a Width parameter value of 4. This overrides the default Width value of 8 that was defined in the Mux module.

Type Parameters in Verilog and SystemVerilog

Type parameters enable modules, interfaces, and programs to have ports or data objects with different types. They are defined using the type keyword followed by the name of the parameter.

Consider the following code that defines a module named MyAdder with a type parameter named T, which defaults to MyType. It also has two input ports named myInput1 and myInput2, and one output port named myOutput. The type of these ports is specified by the T parameter:

module MyAdder #(
  type T = MyType
) (
  input  T myInput1, myInput2,
  output T myOutput
);
  assign myOutput = myInput1 + myInput2; 
endmodule

The T parameter allows for different types to be used as input and output ports for the MyAdder module. The default value for the T parameter is MyType.

Type parameters can be utilized to instantiate a module with a specific type. For instance, the following code instantiates the MyAdder module with an integer type and a real type:

MyAdder #(int)  intAdder (
  // ...
);
MyAdder #(real) realAdder (
  // ...
);

In the above code, intAdder is an instance of the MyAdder module with integer type, and realAdder is an instance of the MyAdder module with real type. This way, the same module can be instantiated with different data types as required.

Localparam Constants in Verilog and SystemVerilog

Localparam constants are constants that cannot be modified by defparam statements or instance parameter value assignments. They are defined using the localparam keyword followed by the name and value of the constant.

Localparam constants are helpful when you need to set a value that should not be altered by the user. For instance, consider the following code that defines a Memory module with a parameter named EntryNum and a localparam named AddrWidth. The localparam is utilized to set the width of the address bus based on the value of the EntryNum parameter, which should be calculated, and the user should not modify it.

module Memory #(
  parameter  int EntryNum  = 8,
  localparam int AddrWidth = $clog2(EntryNum))
)(
  // ...
);
  // ...
endmodule

In the above code, $clog2 is a system task that returns the smallest integer value greater than or equal to the logarithm of the argument to the base-2. Therefore, the AddrWidth localparam sets the width of the address bus to the smallest possible width that can address all entries in the memory module.

Using localparam constants is a good practice when you want to make sure that certain values remain constant throughout the design and should not be altered by the user.

Specparam Constants in Verilog and SystemVerilog

Specparam constants are used to provide timing and delay values for Verilog and SystemVerilog simulations. They are declared within a module or a specify block and are used to override the timing and delay values. Specparam constants are defined using the specparam keyword followed by the name and value of the constant.

For instance, consider the following code that defines a specparam constant named Delay with a value of 10:

specparam Delay = 10;

In the above code, Delay is a specparam constant that provides a delay value of 10.

Specparam constants can only be overridden using SDF (Standard Delay Format) annotations. SDF annotations are used to specify the timing and delay information for individual elements of the design and are used to produce accurate simulation results.

Const Constants in SystemVerilog

SystemVerilog introduced the const keyword for defining constants that can be set during simulation, unlike parameter constants. The syntax for defining const constants includes the const keyword followed by the name and value of the constant. Const constants allow for the use of hierarchy names and act like a read-only variable that can be set in an automatic task.

Consider the following code that defines a const constant named Option with a value of a.b.c:

const myType Option = a.b.c;

In the above code, Option is a const constant that has the value a.b.c. The hierarchy name a.b.c can be assigned to the Option constant.

During simulation, const constants cannot be written, but they can be set in an automatic task. Automatic tasks are triggered by events, such as the initialization of a variable, and can be used to set the const constants. This feature provides flexibility during simulation by allowing const constants to be modified while maintaining their constancy during the design.

Conclusion

Understanding the different types of Verilog and SystemVerilog constants is crucial in developing effective hardware designs that are flexible, robust, and easy to modify. By incorporating parameter, localparam, specparam, and type parameter constants, designers can ensure that values remain constant and that modules have the flexibility to work with different types.