Shou-Li Hsu

Learn how to design frequency dividers in Verilog and SystemVerilog with examples for dividing by 2, 4, and 3. Implement a divide by 3 frequency divider using a counter and a comparator.

Learn how to design rising and falling edge detectors, as well as a both edge detector in Verilog and SystemVerilog. Achieve precise control over your signals and advanced functionality in digital circuits.

Learn how to design a register file in Verilog and SystemVerilog. Discover how to handle read/write conflicts and build custom circuits for your application.

Learn how to design Pulse-Width Modulation (PWM) circuits in Verilog and SystemVerilog with a simplified digital counter and a comparator. Control power delivery to loads with ease.

Learn how to design a single-port memory in Verilog and SystemVerilog with a write port and read port. Also, discover how to add byte-enable memory and a register at the read data path.

Learn how to design Finite State Machines (FSMs) in Verilog and SystemVerilog. Design Moore and Mealy machines with reset signal, using enum and case statements.

Learn how to design a simple Arithmetic Logic Unit (ALU) in Verilog and SystemVerilog that can perform basic arithmetic and logical operations in this tutorial.

Learn how to design decoders in Verilog and SystemVerilog with this tutorial. Build a flexible, parameterized decoder that can handle any number of input bits.

Learn how to design a sign extension module in Verilog and SystemVerilog for digital circuits. Sign extension is used to expand a value to a larger bit width while preserving its sign.

Learn how to design a 4-bit unsigned and signed comparator in Verilog and SystemVerilog. Comparators are useful for comparing inputs and making decisions based on the result.