Shou-Li Hsu

Shou-Li Hsu is a talented circuit designer from Taiwan, experienced in CPU design and VLSI. He's currently working as a CPU RTL design engineer in a tech company.

Verilog and SystemVerilog Arrays: Packed and Unpacked

This tutorial explores Verilog and SystemVerilog packed and unpacked arrays, highlighting their differences, how to define and manipulate them, and their applications in hardware design and verification.

Guide to Verilog and SystemVerilog Constants

Verilog and SystemVerilog constants are essential for creating flexible, robust, and easily modifiable hardware designs. This tutorial explores different types of SystemVerilog constants, including parameter, localparam, specparam, type parameter, and const constants.

Understanding SystemVerilog Unions: A Beginner's Guide

Unlock new levels of flexibility and control in circuit design with SystemVerilog unions. Learn types and how to use them for efficient, type-safe code.

Understanding SystemVerilog Structures Data Type

Learn how SystemVerilog structures provide an efficient way to organize and store complex data types for circuit design. Understand packed and unpacked structures and assigning values.

SystemVerilog Enumerations Data Type: A Beginner's Guide

In this blog post, we'll be discussing SystemVerilog enumerations - an essential data type in the language. We will cover the basics of enumerations, including their syntax, uses, and methods.

A Guide to Understanding SystemVerilog User-Defined Types

This tutorial covers the basics of user-defined types in SystemVerilog, including the different types available, how to declare them, and how to use them in your designs.

Understanding SystemVerilog's Event Data Type

Learn about the event data type in SystemVerilog and how to use it to signal other processes or threads when a certain condition has occurred. Create a persistent triggered state using events.

Understanding the SystemVerilog String Data Type

SystemVerilog's string data type stores and manipulates text data. It supports arbitrary-length strings and built-in methods like len(), putc(), toupper(), and compare(). These simplify working with text data in SystemVerilog design.

Understanding the Chandle Data Type in SystemVerilog

Learn about the chandle data type in SystemVerilog, which is used to represent storage for pointers passed using the Direct Programming Interface (DPI). This data type is an important tool for interfacing SystemVerilog with external languages and libraries.

Real, Shortreal, and Realtime Data Types in Verilog and SystemVerilog

Learn about the real, shortreal, and realtime data types in Verilog and SystemVerilog, and how they are used to represent floating-point numbers and model time in a simulation.