Shou-Li Hsu

Shou-Li Hsu is a talented circuit designer from Taiwan, experienced in CPU design and VLSI. He's currently working as a CPU RTL design engineer in a tech company.

Mastering $display and $write in Verilog and SystemVerilog

Dive into the world of Verilog and SystemVerilog. This post simplifies $display and $write tasks, and decodes escape sequences, equipping you with the essential skills for your coding projects.

Programmable Logic Array (PLA) Tasks in Verilog and SystemVerilog

Explore the essentials of Programmable Logic Array (PLA) tasks in Verilog and SystemVerilog. From the syntax and array types to real-world implementation with a full adder, get an in-depth guide.

Verilog and SystemVerilog Stochastic Analysis Functions

Learn how to manage queues in Verilog and SystemVerilog using stochastic analysis functions. Create, modify, and gather queue information for digital design and verification.

Verilog/SystemVerilog Random and Distribution Functions

Dive into probabilistic distribution functions in Verilog & SystemVerilog. Harness $random, $urandom, & distribution functions for versatile simulations.

Delving into SystemVerilog's Built-In Coverage Functions

Discover SystemVerilog coverage functions for better test coverage, merging and saving coverage data, and ensuring your designs meet quality standards.

Global Clocking Sampled Value Functions in Verilog and SystemVerilog

Master global clocking functions in Verilog & SystemVerilog to create efficient assertions, assumptions, and covers for reliable design verification.

Acing Verilog and SystemVerilog Sampled Value Functions

Delve into Verilog and SystemVerilog sampled value functions to strengthen your hardware design skills. Master $sampled, $rose, $fell, and other functions for powerful signal analysis.

Mastering Assertion Control in Verilog and SystemVerilog

Master assertion control in Verilog and SystemVerilog with powerful functions like $assertcontrol, $asserton, $assertoff, and more. Enhance design management and action block execution for reliable, efficient systems.

Verilog and SystemVerilog Bit Vector Functions

Unlock the power of Verilog and SystemVerilog bit vector functions. Learn about $countbits, $countones, $onehot, $onehot0, and $isunknown to enhance your hardware design expertise.

Mastering Math Functions in Verilog and SystemVerilog

Get to know math functions in Verilog and SystemVerilog with our simple tutorial. Explore functions such as trigonometry, logarithms, and exponentials to enhance your digital designs.