Designing Latches in Verilog and SystemVerilog

Learn to design a simple level-sensitive latch using SystemVerilog's always_latch construct. Understand how latches retain state based on the input signal, even after it's removed.

Designing Shift Registers in Verilog and SystemVerilog

Learn to design a 4-bit PIPO shift register in Verilog and SystemVerilog. Use this building block to create complex digital circuits. Read on for a simple tutorial.

Designing Priority Encoders in Verilog and SystemVerilog

Priority encoders determine highest-priority input. Basic design uses for loop; enable input design adds enable signal condition. Both can be implemented in Verilog and SystemVerilog.

Designing Adders in Verilog and SystemVerilog

Learn how to design half adder, full adder, and carry ripple adder in Verilog and SystemVerilog. See examples of how to use these digital circuits to add binary numbers.

Designing Counters in Verilog and SystemVerilog

Learn how to design up-counters, bidirectional counters, and gray counters in Verilog and SystemVerilog.